As Samsung Electronics competes with TSMC and Intel to develop advanced ultra-fine semiconductor processes, the company is set to introduce the highly complex, game-changing Backside Power Delivery Network (BSPDN) technology into its 2-nanometer process for mass production next year.
According to industry sources on Feb. 28, Samsung Electronics confirmed that the backside power supply technology it is developing has achieved metrics that surpass the initial targets in the early stages. By using two different ARM cores, Samsung reduced chip areas by 10% and 19%, respectively, and succeeded in enhancing chip performance and frequency efficiency by single-digit percentages.
Backside power delivery network is a new semiconductor process that has yet to be commercialized. Traditionally, power supply lines have been positioned on the front side of the wafer, where the circuits are drawn for processing convenience. However, as circuits are printed more finely, it has become challenging to inscribe both circuits and power lines on the same surface. The decreasing gap between circuits has led to interference, adding to the manufacturing and design complexities.
BSPDN can overcome these limitations. By placing power lines on the back of the wafer, it separates the circuit and power supply areas, thereby maximizing power efficiency and enhancing semiconductor performance. It also proves effective in reducing the overall chip area and is particularly expected to contribute to the miniaturization of chip sizes in the production of mobile application processors (APs).
With Samsung Electronics exceeding its target metrics in the early development stages, it is likely that the commercialization of the technology, initially scheduled for around 2027, will be expedited. Previously, it was reported that Samsung would introduce the backside power supply technology starting from the 1.7nm process. However, it is now expected that the company will revise its roadmap and introduce the technology as early as next year when mass production of the 2nm process begins.
Intel, considered a leader in backside power delivery technology, plans to mass-produce semiconductors using BSPDN technology within this year, targeting its 2nm-class 20A process. It has also introduced its own brand, PowerVia, to emphasize the excellence of its backside power delivery technology. TSMC plans to apply the technology in processes below 2nm, with development aimed for completion by 2026.
